ANTI-TAMPER DIGITAL CLOCKS - AN OVERVIEW

Anti-Tamper Digital Clocks - An Overview

Anti-Tamper Digital Clocks - An Overview

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A no-clock-existing problem could possibly be detected once the circuit Using the longest propagation hold off is activated. This result in might possibly be employed by asynchronous circuits to respond straight away or simply a point out bit is often set for your procedure to respond later in the event the clock comes again on.

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23. A method for detecting voltage tampering, comprising: furnishing a plurality of resettable hold off line segments, whereby resettable hold off line segments in between a resettable delay line segment associated with a minimal delay time along with a resettable hold off line segment connected with a maximum delay time are Each and every related to discretely rising delay periods;

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four. The method for detecting clock tampering as described in declare 1, wherein the Examine circuit determines regardless of whether the number of kinds during the plurality of delayed monotone indicators differs from the h2o stage range by in excess of a predetermined threshold.

39. The equipment for detecting voltage tampering as defined in claim 37, wherein the Assess circuit is brought on by a clock edge at an conclusion of the Examine period of time.

The monotone 0 to one transition might be reached by introducing reset operators. Each reset operator may reset the respective delay line in the sensing circuit during the reset period to some regarded state unbiased of any setup-violations, while the circuit senses in the analysis section. With no reset operators, the sensing circuit that detects slower than expected frequencies can be in an unknown state.

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31. The apparatus for detecting voltage tampering as defined in assert thirty, more comprising: means for resetting the signifies for delaying the monotone signal in the course of a reset time period, whereby the reset time period is before the Appraise time frame.

18. The equipment for detecting clock tampering as defined in declare 15, wherein the Examine circuit establishes no matter if the volume of types during the plurality of delayed monotone alerts differs from a water amount number by greater than a predetermined threshold to detect a clock fault.

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